Large integrated circuits (VSLI) are usually designed from components provided by a library of circuit modules. The design process involves choosing the correct modules and connecting the modules together to provide the desired functionality. A significant fraction of the improvements in the costs and functions of custom integrated circuits is related to the use of well-characterized libraries of standard cells.
In production, there is always a finite error rate. Hence, the integrated circuits must be tested after the fabrication process to assure that the individual chips do not contain fatal fabrication errors. The testing process involves applying a number of test vectors to the integrated circuit. Each test vector specifies the input signals to be applied to the various inputs of the circuit. The tester then examines the outputs generated by the circuit to determine if the circuit is functioning properly. As circuits become more complex, the number of test vectors needed to thoroughly test the circuit becomes increasingly large, and the testing procedure becomes too costly.
If a chip is found to be defective, it may still be repairable if the location of the fault is known. For example, some chip designs include redundant modules that can be connected in a bus to replace a non-functioning module that is currently connected to the bus. Hence, it would be advantageous to be able to test the individual modules to determine which module is responsible for the fault.
Broadly, it is the object of the present invention to provide an improved integrated circuit design that facilitates testing of the integrated circuit.
It is a further object of the present invention to provide an integrated circuit design that allows individual modules to be tested separately.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.